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M66239FP
High Speed Standard Clock Generator With Frequency Synthesizer
REJ03E0002-0100 Rev.1.00 Mar 16, 2005
Description
M66239FP is high speed synchronizing clock generator with frequency synthesizer which is fabricated by high performance silicon gate CMOS process technology. It is able to output clock in sync with external trigger. And it features excellent synchronizing precision (sync accuracy: jitter) over a wide range frequency band. Also, it has frequency synthesizer function which is able to modulate input frequency by resister setting before normal operation. Frequency modulation resolution is high accuracy 0.01%. And in order to process the Y/M/C/K printing signal processing by 1 chip, M66239FP integrate fore synchronizing clock generator macro with frequency synthesizer function. Also, this part can use various applications as frequency synthesizer LSI.
Features
* * * * Power supply voltage: Single 3.3 V Frequency band: 28 MHz to 100 MHz Synchronizing precision (jitter): T = 1.5 ns Output clock type (1) Sync clock output (CKO) (2) Sync clock output inverted CKO (CKOB) (3) One-shot pulse output (PULSE) (4) Continuous clock output (CLKO: asynchronous to trigger) Trigger edge: Polarity (positive/negative) selectable Output clock phase control: T/8 step resolution (T: clock period) Frequency synthesizer type (1) Offset type modulation (2) Triangle type modulation (3) Polygon type modulation Frequency modulation resolution: 0.01% Output clock center frequency modulation: 0.01% step/Maximum 2.55% Output clock peak frequency modulation: 0.01% step/Maximum 2.55% Output clock modulation period: 16 bit resister setting Output clock modulation start position: 10 bit resister setting Output clock disable function: Disable CKOB and PULSE by OE pin control Integrated 4 synchronizing clock generator macro with frequency synthesizer function
* * *
* * * * * * *
Application
Digital color copier/Digital color laser beam printer
Rev.1.00 Mar 16, 2005 page 1 of 23
M66239FP
Block Diagram
SCLK1/SENABLE1/SDATA1 MCLK1 TR1/MODE1
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO1 CKO1 CKOB1 PULSE1
SCLK2/SENABLE2/SDATA2 MCLK2 TR2/MODE2
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO2 CKO2 CKOB2 PULSE2
SCLK3/SENABLE3/SDATA3 MCLK3 TR3/MODE3
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO3 CKO3 CKOB3 PULSE3
SCLK4/SENABLE4/SDATA4 MCLK4 TR4/MODE4
Serial input register
Frequency modulation circuit
Sync clock generator
CLKO4 CKO4 CKOB4 PULSE4
Rev.1.00 Mar 16, 2005 page 2 of 23
M66239FP
Pin Configuration
1st-line 4th-line
143
142
140
139
138
137
135
133
132
130
129
128
127
125
123
122
120
119
118
117
115
113
112
110
TESTP1 TESTN1 DACVCC DACGND RESET1 TEST<0> TEST<1> OE1 PLLVCC PLLGND PLLVCC PLLGND AVCC AGND MODE1 MCLK1 DVCC DGND DGND DVCC MCLK2 MODE2 AGND AVCC PLLGND PLLVCC PLLGND PLLVCC OE2 TEST<2> TEST<3> RESET2 DACGND DACVCC TESTN2 TESTP2
109
136
134
131
126
124
121
144
141
116
114
111
SCLK1 SENABLE1 SDATAIN1 SDATAOUT1 DACGND DACVCC TR1 CKO1 AGND AVCC CKOB1 PULSE1 DGND DVCC CLKO1 FSET1<2> FSET1<1> FSET1<0> FSET4<0> FSET4<1> FSET4<2> CLKO4 DVCC DGND PULSE4 CKOB4 AVCC AGND CKO4 TR4 DACVCC DACGND SDATAOUT4 SDATAIN4 SENABLE4 SCLK4
1 2 3 4 5 6 7 8 9 10 11 12
108 107 106 105 104 103 102 101 100 99 98 97
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TESTP4 TESTN4 DACVCC DACGND RESET4 TEST<7> TEST<6> OE4 PLLVCC PLLGND PLLVCC PLLGND AVCC AGND MODE4 MCLK4 DVCC DGND DGND DVCC MCLK3 MODE3 AGND AVCC PLLGND PLLVCC PLLGND PLLVCC OE3 TEST<5> TEST<4> RESET3 DACGND DACVCC TESTN3 TESTP3
M66239FP XXXXXX
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Rev.1.00 Mar 16, 2005 page 3 of 23
SCLK2 SENABLE2 SDATAIN2 SDATAOUT2 DACGND DACVCC TR2 CKO2 AGND AVCC CKOB2 PULSE2 DGND DVCC CLKO2 FSET2<2> FSET2<1> FSET2<0> FSET3<0> FSET3<1> FSET3<2> CLKO3 DVCC DGND PULSE3 CKOB3 AVCC AGND CKO3 TR3 DACVCC DACGND SDATAOUT3 SDATAIN3 SENABLE3 SCLK3
2nd-line Package 144P6Q (Top view)
3rd-line
72
M66239FP
Pin Description
Pin Name MCLK SCLK SENABLE SDATAIN RESET FSET<2:0> MODE TR CLKO CKO CKOB PULSE SDATAOUT OE I/O I I I I I I I I O O O O O I Input clock. Serial resister clock input. Serial resister enable input. H level: disable, L level: enable Serial resister data input. System reset input. When set to "L", system reset function. Reset function initialize all resister data to the default settings. Frequency range settings correspond to MCLK frequency. Trigger edge polarity (positive/negative) select. H level: negative edge mode, L level: positive edge mode Trigger input for clock outputs. Continuous clock output. CLKO is asynchronous clock output to trigger. Sync. clock output. Synchronized with trigger signal. Sync. clock output. Synchronized with trigger signal. CKOB is inverted clock of CKO. Sync. clock output. Synchronized with trigger signal. PULSE is one-shot pulse synchronized with CKO. Serial resister data output. Output enable control. H level: CKOB and PULSE will be disabled. L level: All clock outputs will be enabled. Test control input. Set to "L". Test control input. Set to open. Digital block VDD and GND. Analog block VDD and GND. PLL block VDD and GND. DA converter VDD and GND. Function
TEST<7:0> TESTP<4:1> TESTN<4:1> DVCC DGND AVCC AGND PLL VCC PLL GND DAC VCC DAC GND
I O I I I I
Rev.1.00 Mar 16, 2005 page 4 of 23
M66239FP
Whole Block Diagram
CLKO1 CKO1 CKOB1 PULSE1 CLKO2 CKO2 CKOB2 PULSE2 CLKO3 CKO3 CKOB3 PULSE3 CLKO4 CKO4 CKOB4 PULSE4
MCLK1
Y-line channel
MCLK2
M-line channel
MCLK3
C-line channel
MCLK4
K-line channel
Unit Channel Block Diagram
Frequency modulation circuit
CLKO
MCLK
Clock generator
FSET<2:0>
Frequency control Sync clock generator
CKO
CKOB
SENABLE SDATAIN SCLK SDATAOUT RESET Serial input register PULSE TEST mode control
TEST<7:0>
MODE
Rev.1.00 Mar 16, 2005 page 5 of 23
OE
TR
M66239FP
Function Summary
Sync Clock Generation Function M66239FP has standard clock generator function, it is able to output clock in sync with external trigger TR. And it features excellent synchronizing precision (sync accuracy: jitter) over a wide range frequency band. Sync clock output timing is determined by trigger input signal edge. Trigger edge polarity (positive/negative) is selectable by MODE input. Time-lag between trigger input signal edge and sync clock output equals the sum of clock input signal "L" pulse width and M66239FP internal delay. Variation in this lag (t) is 1.5ns, ensuring excellent synchronizing accuracy. There are three types of outputs: synchronous clock output (CKO), synchronous clock inverted output (CKOB), and one-shot pulse output (PULSE). Synchronous clock output CKO is the same frequency as clock input signal MCLK. Synchronous clock inverted output CKOB is inverted signal of sync clock CKO. PULSE is one-shot pulse output which is almost equal to two cycles. All three sync outputs are suspended when trigger input signal is on "H" level when MODE is "H", and "L" level when MODE is "L" level. During these period, CKO and PULSE stay on "L" level, CKOB stay on "H" level. Also, start phase of 3 sync. clocks are controlled by T/8 steps (T: Clock Period). T/8 steps resolution is controlled by serial resister setting. M66239FP integrate four synchronizing clock generator macro with frequency synthesizer function.
Frequency Modulation Function M66239FP is able to modulate sync. clock frequency. Frequency modulation profile is controlled by serial resister. Serial resister is controlled by serial input clock (SCLK), serial input enable (SENABLE) and serial input data (SDATAIN). When SENABLE is "L" level, SDATAIN is able to write to serial input resister by SCLK. SDATAIN is composed by 4 bit address + 3 bit W/R distinction + 16 bit resister data. After write operation completed, it can be able to confirm the resister status using read operation to serial input resister. Resister setting is as follows. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) 3rd.pole position (3rdPole) 4th.pole position (4thPole) 1st.Pole frequency (f1stPole) 3rd.Pole frequency (f3rdPole) : Resister 1 : Resister 2 : Resister 3 : Resister 4 : Resister 5 : Resister 6 : Resister 7 : Resister 8 : Resister 9 : Resister 10 : Resister 11
There are four operation modes, center frequency offset type modulation (mode1), triangle type modulation (mode2 and 3), and polygon type modulation (mode4).
Rev.1.00 Mar 16, 2005 page 6 of 23
M66239FP
Sync. Clock Generation Operation Timing
Trigger Mode 1 (Negative edge operation: MODE = "H")
1/fIN MCLK tw(TR) TR tsp(CKO) CKO tsp(CKO) CKOB tss(CKO) t PULSE tss(PULSE) tw(PULSE)
VOH VOL Vcc 0V Vcc 0V
t tss(CKO) t
VOH VOL VOH VOL
Figure 1 Trigger Mode 1
Trigger Mode 2 (Positive edge operation: MODE = "L")
1/fIN MCLK tw(TR) TR tsp(CKO) CKO tsp(CKO) CKOB tss(CKO) tss(CKO) t
VOH VOL Vcc 0V Vcc 0V
t
VOH VOL
t PULSE tss(PULSE) tw(PULSE)
VOH VOL
Figure 2 Trigger Mode 2 Notes: 1. tss (CKO, CKOB and PULSE) equals the sum of input clock "L" width and . Value refers to internal delay in M66239FP. Under environment where temperature and VCC do not change, value and tss are kept constant approximately. Dispersion of tss under such conditions is defined as t (synchronizing precision: jitter). 2. Outputs (CKO, CKOB and PULSE) are unknown until twice trigger pulse input TR reaches after power-on. 3. Internal trigger signal is generated by EXOR of TR and MODE signal.
Rev.1.00 Mar 16, 2005 page 7 of 23
M66239FP
Sync. Clock Phase Timing
M66239FP is able to control the phase of sync clock outputs (CKO, CKOB, PULSE) as each T/8 step. (T: clock period) This phase shift control is set up by serial input resister No. 13. Also, 1st edge phase (= (1) position) of sync clock outputs is not shifted, and 2nd edge phase (= (2) position) of sync clock outputs is either not shifted position or resister set position, after 3rd edge phase (= (3) position) of sync clock outputs is shift as resister settings. CLKO output can not use this phase shift function because CLKO is asynchronous clock output to trigger.
MCLK TR CKO CKOB PULSE CLKO
TR (1)
Phase shift = 0 set Phase shift = (T/8)x1 set Phase shift = (T/8)x2 set Phase shift = (T/8)x3 set
T
(2)
(3)
CKO
Phase shift = (T/8)x4 set Phase shift = (T/8)x5 set Phase shift = (T/8)x6 set Phase shift = (T/8)x7 set
each T/8 step Notes: 1. 1st edge phase of sync clock output is not shifted. 2nd edge phase of sync clock output is either not shifted position or resistor set position, 3rd edge phase of sync clock output is shift as resistor settings. 2. It can set T/8 step resolution, but if T/8 is less than synchronizing precision (jitter) +/- 1.5 ns, it may be not able to realize such high step resolution. T/8 is not guarantee value which is taken into account the jitter and noise.
tss(CKO)
Figure 3 Sync. Clock Phase Timing
Rev.1.00 Mar 16, 2005 page 8 of 23
M66239FP
Frequency Modulation Operation Timing
Function Mode 1 Mode 1 is frequency offset type modulation. Output clock frequency keep Fcenter-freqency. Frequency modulation is set by serial input resister. (1) Operation mode (2) Frequency modulation start position (Tstart) (3) Output center frequency (fcenter)
MCLK TR CKO Output clock frequency Fpeak+ Fcenter
: Resister 1 : Resister 3 : Resister 4
Tstart
Fpeak- Modulation start Note: 1. Until next TR input, output clock frequency keep "Fcenter".
Figure 4 Operation Timing of Mode 1
Rev.1.00 Mar 16, 2005 page 9 of 23
M66239FP Function Mode 2 Mode 2 is triangle modulation type as following. Frequency modulation is set by serial input resister. (1) (2) (3) (4) (5) (6) (7) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) : Resister 1 : Resister 2 : Resister 3 : Resister 4 : Resister 5 : Resister 6 : Resister 7
MCLK TR CKO Output clock frequency Fpeak+ Tspace1 Fcenter Tspace2 Fpeak- Modulation start 1st Pole 2nd Pole Modulation end Tspace6
Tstart Trate
Notes: 1. Each Pole position (cycle number) is defined by Tstart position. 2. Until next TR input, output clock frequency keep "Fcenter".
Figure 5 Operation Timing of Mode 2
Rev.1.00 Mar 16, 2005 page 10 of 23
M66239FP Function Mode 3 Mode 3 is triangle modulation type as following. Frequency modulation is set by serial input resister. (1) (2) (3) (4) (5) (6) (7) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) : Resister 1 : Resister 2 : Resister 3 : Resister 4 : Resister 5 : Resister 6 : Resister 7
MCLK TR CKO Output clock frequency Fpeak+ Fcenter
Tstart Trate
Fpeak-
Tspace1 Modulation start 1st Pole
Tspace2 2nd Pole
Tspace6 Modulation end
Notes: 1. Each Pole position (cycle number) is defined by Tstart position. 2. Until next TR input, output clock frequency keep "Fcenter".
Figure 6 Operation Timing of Mode 3
Rev.1.00 Mar 16, 2005 page 11 of 23
M66239FP Function Mode 4 Mode 4 is polygon modulation type as following. Frequency modulation is set by serial input resister. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) 3rd.pole position (3rdPole) 4th.pole position (4thPole) 1st.Pole frequency (f1stPole) 3rd.Pole frequency (f3rdPole) : Resister 1 : Resister 2 : Resister 3 : Resister 4 : Resister 5 : Resister 6 : Resister 7 : Resister 8 : Resister 9 : Resister 10 : Resister 11
MCLK TR CKO Output clock frequency Fpeak+ F3rdpole Fcenter F1stpole Fpeak- Tspace1 Tspace2 Tspace3 Tspace4 Tspace5
Tstart Trate
Modulation start 1st Pole
2nd Pole 3rd Pole
4th Pole
Modulation end
Notes: 1. Each Pole position (cycle number) is defined by Tstart position. 2. Until next TR input, output clock frequency keep "Fcenter". 3. F3rdpole and Fpeak+ must set higher frequency than Fcenter. F1stpole and Fpeak- must set lower frequency than Fcenter.
Figure 7.1 Operation Timing of Mode 4 (1)
Rev.1.00 Mar 16, 2005 page 12 of 23
M66239FP Function Mode 4 (cont.) Mode 4 is polygon modulation type as following. Frequency modulation is set by serial input resister. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Operation mode Frequency modulation period (Trate) Frequency modulation start position (Tstart) Output center frequency (fcenter) Output peak frequency (fpeak) 1st.pole position (1stPole) 2nd.pole position (2ndPole) 3rd.pole position (3rdPole) 4th.pole position (4thPole) 1st.Pole frequency (f1stPole) 3rd.Pole frequency (f3rdPole) : Resister 1 : Resister 2 : Resister 3 : Resister 4 : Resister 5 : Resister 6 : Resister 7 : Resister 8 : Resister 9 : Resister 10 : Resister 11
MCLK TR CKO Output clock frequency Fpeak+ F1stpole Fcenter F3rdpole Fpeak- Tspace1 Tspace2 Tspace3 Tspace4 Tspace5
Tstart Trate
Modulation start 1st Pole
2nd Pole 3rd Pole
4th Pole
Modulation end
Notes: 1. Each Pole position (cycle number) is defined by Tstart position. 2. Until next TR input, output clock frequency keep "Fcenter". 3. F1stpole and Fpeak+ must set higher frequency than Fcenter. F3rdpole and Fpeak- must set lower frequency than Fcenter.
Figure 7.2 Operation Timing of Mode 4 (2)
Rev.1.00 Mar 16, 2005 page 13 of 23
M66239FP
CLKO Operation Timing
The CLKO output is the continuation clock output that frequency modulation is worked like CKO but to be in the asynchronous relation with TR. Of the operation timing specified in operation mode 4 in the figure below by it but the other operation mode is same. Also, because CLKO is continuation clock output before synchronous clock generation circuit, phase relation during 4 channel is not guaranteed.
MCLK TR CKO CLKO Output clock frequency Fpeak+ F3rdpole Fcenter F1stpole Fpeak- Tspace1 Tspace2 Tspace3 Tspace4 Tspace5
Tstart Trate
Modulation start Output clock frequency Fpeak+ F3rdpole Fcenter F1stpole Fpeak- 1st Pole Tstart
2nd Pole 3rd Pole Trate
4th Pole
Modulation end
Tspace1 Tspace2
Tspace3
Tspace4
Tspace5
Modulation start 1st Pole
2nd Pole 3rd Pole
4th Pole
Modulation end
Figure 8 CKO (upper) and CLKO (lower)
Rev.1.00 Mar 16, 2005 page 14 of 23
M66239FP
Frequency Modulation Resister Setting (Write Operation)
Write Operation Frequency modulation is set by serial input resister. Serial input resister is controlled by serial input clock (SCLK), serial input enable (SENABLE) and serial input data (SDATAIN). When SENABLE is "L" level, SDATAIN is written to serial input resister by SCLK. SDATAIN is composed by 4 bit address + 3 bit W/R distinction data + 16 bit resister data. After SENABLE change to "H", more than 20 dummy SLCK cycle is needed.
SENABLE tDS SCLK tDH tDS SDATAIN A0 A1 A2 A3 H H H LSB D0 D1 D2 MSB D13 D14 D15 20 cycles dummy input tDH
4bit address
16bit data
For write operation, set to "H" 3 cycles continuously.
Figure 9 Frequency Modulation Resister Setting (Write Operation)
Rev.1.00 Mar 16, 2005 page 15 of 23
M66239FP
Frequency Modulation Resister
Resister Name Resister 1 Resister 2 Resister 3 Resister 4 Address Function Operation mode Modulation period Modulation start position Center frequency
A3
Bit 3 bit 16 bit 10 bit 9 bit
Setting Range
D15 *** D0 D15
Default Value
*** D0
A0 Number
0000 0001 0010 0011
min 0000000000000001 max 0000000000000100 min max min max min max 0000010111011100 1111111111111111 0000000001100100 0000001111111111 0000000000000000 0000000111111111
0000000000000001(1 dec)
* Mode1 when 1 dec
Unit 1LSB --
0010000000000000(8192 dec) MCLK cycle 0000000100000000(256 dec) 0000000100000000(256 dec) MCLK cycle MCLK frequency
* -2.55% when min. value * +2.55% when max. value
x0.01% * 0% when 256 dec * Modulate to + side more than 256 dec * Modulate to - side less than 256 dec
* 2.55% when 255 dec
Resister 5
Peak frequency
0100
8 bit
min 0000000000011110 max 0000000011111111
* 0.30% when min. value * 2.55% when max. value
0000000011111111(255 dec)
MCLK frequency x0.01%
1st-pole position Resister 7 2nd-pole position Resister 8 3rd-pole position Resister 9 4th-pole position Resister 10 1st-pole frequency (Mode 4) Resister 11 3rd-pole frequency (Mode 4) Resister 12 Modulation resolution
Resister 6
0101 0110 0111 1000 1001
16 bit 16 bit 16 bit 16 bit 9 bit
min max min max min max min max min max
0000000111110100 1001111111111111 0000000111110100 1001111111111111 0000000111110100 1001111111111111 0000000111110100 1001111111111111 0000000000000000 0000000111111111
0000011001100110(1638 dec) MCLK cycle 0000110011001100(3276 dec) MCLK cycle 0001001100110010(4914 dec) MCLK cycle 0001100110011000(6552 dec) MCLK cycle 0000000010000000(128 dec)
* -1.28% when 128 dec
MCLK frequency x0.01%
* -2.55% when min. value * +2.55% when max. value
1010
9 bit
min 0000000000000000 max 0000000111111111
* -2.55% when min. value * +2.55% when max. value
0000000110000000(384 dec)
* +1.28% when 384 dec
MCLK frequency x0.01%
1011
1 bit
min 0000000000000000 max 0000000000000001
* 0.01% mode when min. * 0.005% mode when max.
0000000000000000(0 dec)
* 0.01% mode when 0 dec
--
Resister 13 Output phase control
1100
3 bit
min 0000000000000000 max 0000000000000111
* Delay 0 when min. * Delay 7T/8 when max.
0000000000000000(0 dec)
* Delay 0 when 0 dec
T/8 (Clock cycle)
Notes: 1. Set to the following value for resister 1. * For operation mode 1: "0000000000000001" * For operation mode 2: "0000000000000010" * For operation mode 3: "0000000000000011" * For operation mode 4: "0000000000000100" 2. Resister 12 must not change. 3. Above table intend to setting available value of resister, practical limits are described in page 20. 4. Resister 13 is for phase control of sync clock output. 5. If the default value of above resister use, write operation to all resister must be done. 6. Resister 6 to 9 refer to following. * 1st Pole = Tspace1 * 2nd Pole = Tspace1 + Tspace2 * 3rd Pole = Tspace1 + Tspace2 + Tspace3 * 4th Pole = Tspace1 + Tspace2 + Tspace3 + Tspace4
Rev.1.00 Mar 16, 2005 page 16 of 23
M66239FP
Frequency Modulation Resister Setting (Read Operation)
Read Operation After write operation completed, it can confirm the resister status using read operation to serial input resister. When SENABLE is "L" level, SDATAIN is written to serial input resister by SCLK. SDATAIN is composed by 4 bit address + 3 bit W/R distinction data. After SENABLE change to "H", more than 20 dummy SLCK cycle is needed.
SENABLE tDS
(1) (2) (3) (4) (5) (6) (7) (8)
tDH
SCLK tDH tDS SDATAIN A0 A1 A2 A3 L L L 20 cycles dummy input
4bit address For write operation, set to "L" 3 cycles continuously. LSB SDATAOUT D0 D1 D2 16bit data MSB D13 D14 D15
Figure 10 Frequency Modulation Resister Setting (Read Operation)
Rev.1.00 Mar 16, 2005 page 17 of 23
M66239FP
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage Storage temperature Symbol Vcc VI VO Tstg Ratings -0.3 to +4.6 -0.3 to Vcc+0.3 -0.3 to Vcc+0.3 -55 to +150
1
Unit V V V C
Conditions
Power dissipation Pd 2500 * mW ja = 30C/W, Ta = 50C Note: 1. ja should be less than 30C/W, Tjmax should be less than 125C. When ja = 30C/W and Tjmax is 125C, Ta(max) will be 50C. PCB needs over 4 layers, over 100 mm x 100 mm size, over 70% Cu occupied ratio (average value of each layer) roughly. Please contact to our sales division when you design PCB layout.
Recommended Operating Conditions
Item Supply voltage Supply voltage Input voltage Output voltage Operating temperature Symbol Vcc GND VI VO Topr Min 3.15 -- 0 0 0 Typ 3.3 0 -- -- -- Max 3.46 -- Vcc Vcc 50 Unit V V V V C Conditions
DC Characteristics
(Ta = 0 to +50C, Vcc = 3.15 to 3.46V, GND = 0V)
Item "H" input voltage "L" input voltage "H" output voltage "L" output voltage Supply current (static) Supply current (active) Symbol VIH VIL VOH VOL Icc (s) Icc (a) Min 2.0 -- 2.4 -- -- -- -- -- -- "H" input current "L" input current Input capacitance IIH IIL CI -- -- -- Typ -- -- -- -- 55 480 440 350 250 -- -- -- Max -- 0.8 -- 0.4 100 700 -- -- -- 10 -10 10 A A pF Unit V V V V mA mA IOH = -4 mA IOH = 4 mA VI = Vcc or GND fMCLK = 100 MHz, fSCLK = 20 MHz, CL = 10 pF, OE = L fMCLK = 80 MHz, fSCLK = 20 MHz, CL = 10 pF, OE = L fMCLK = 40 MHz, fSCLK = 20 MHz, CL = 10 pF, OE = L fMCLK = 20 MHz, fSCLK = 20 MHz, CL = 10 pF, OE = L VI = Vcc VI = GND Test Conditions
Note: The direction of current flowing to the circuit is specified to be positive. (No sign)
Rev.1.00 Mar 16, 2005 page 18 of 23
M66239FP
Timing Requirements
(Ta = 0 to +50C, Vcc = 3.15 to 3.46V, GND = 0V)
Item MCLK frequency MCLK and SCLK clock duty TR input pulse width MCLK and SCLK input rising time MCLK and SCLK input falling time SDATA, SENABLE set-up time SDATA, SENABLE hold time SCLK frequency Internal PLL lock up time RESET pulse width Symbol fMCLK fDUTY tw(TR) tr tf tDS tDH fSCLK Tplllock tw(RESET) Min 28 45 500 -- -- 5 5 -- -- 1 Typ -- -- -- -- -- -- -- -- -- -- Max 100 55 5 5 -- -- 20 10 -- Unit MHz % ns ns ns ns ns MHz ms s Test Conditions CL = 10 pF
Switching Characteristics
(Ta = 0 to +50C, Vcc = 3.15 to 3.46V, GND = 0V)
Item Synchronizing precision (jitter) Sync. clock CKO output start time Sync. clock CKOB output start time One-shot pulse output start time Sync clock CKO output stop time Sync. clock CKOB output stop time One-shot pulse width Sync. clock CKO output duty Symbol t tss(CKO) tss(CKOB) tss(PULSE) tsp(CKO) tsp(CKOB) tw(PULSE) foDUTY(CKO) Min -- -- -- -- 2 tp-10 40 Typ -- -- -- -- -- -- Max 1.5 tLp+50 tLp+50 40 2 tp+10 60 Unit ns ns ns ns ns % Test Conditions CL = 10 pF
Sync. clock CKOB output duty foDUTY(CKOB) Notes: 1. tp = 1/fIN, tLp = tp x (100 - fDUTY)/100 2. Switching test waveform Input pulse level MCLK: 0 to Vcc, TR: 0 to Vcc Input clock rising time: 3 ns Input clock falling time: 3 ns Criteria Voltage MCLK: Vcc/2, TR: 1.3 V, Sync. clock: Vcc/2
Rev.1.00 Mar 16, 2005 page 19 of 23
M66239FP
Frequency Modulation Characteristics
(Ta = 0 to +50C, Vcc = 3.15 to 3.46V, GND = 0V)
Item Frequency modulation start position Frequency modulation period Center frequency Center frequency resolution Peak frequency (+ side) Peak frequency (- side) Peak frequency resolution 1st.pole position 2nd.pole position 3rd.pole position 4th.pole position Min cycle between 1stPole and Tstart Min cycle between 2ndPole and 1stPole Min cycle between 3rdPole and 2ndPole Min cycle between 4thPole and 3rdPole Min cycle between modulation end-4thPole Min cycle between modulation end-2ndPole (In case of mode 2 or mode 3) 1st.Pole frequency (In case of page 12) 1st.Pole frequency (In case of page 13) 3rd.Pole frequency (In case of page 12) 3rd.Pole frequency (In case of page 13) Symbol Tstart Trate Fcenter Fstep1 Fpeak+ Fpeak- Fstep2 1stPole 2ndPole 3rdPole 4thPole Tspace1 Tspace2 Tspace3 Tspace4 Tspace5 Tspace6 F1stpole F3rdpole Min 100 1500 0 0.01 +0.3 -0.3 0.01
Tstart+500 1stPole+500 2ndPole+500 3rdPole+500
Typ 256 8192 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max 1023 65535 2.55 -- +2.55 -2.55 -- 40959 40959 40959 40959 -- -- -- -- -- --
-Fpeak+0.1 +Fpeak-0.1 +Fpeak-0.1 -Fpeak+0.1
Unit
Cycle Cycle
Test Conditions CL = 10 pF
% % % % %
Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle
500 500 500 500 500 500
Fcenter-0.1 Fcenter+0.1 Fcenter+0.1 Fcenter-0.1
% % % % %
Notes: 1. Regarding Fpeak+/-, F1stpole, F3rdpole higher frequency than Fcenter is specified to be positive (+ sign), lower frequency than Fcenter is specified to be negative (- sign). 2. The above limitations of Fcenter, Fstep1, Fpeak+/-, Fstep2, F1stpole, F3rdpole, 1stPole, 2ndPole, 3rdPole, and 4thPole are setting available vale. Actual output clock is affected PLL jitter, above limitations are not guarantee value which is taken into account the jitter and noise. 3. Minimum specification of modulation period is 1500 cycles, operation mode 4 needs over 2500 cycles.
Frequency Range Setting of Input Clock
FEST<2:0> pins need to set correspond to following table. Table 1 Frequency Range Setting of Input Clock
FSET<2> H H H FSET<1> L L H FSET<0> L H L
Input Clock Frequency (MHz) 28 to 60 60 to 80 80 to 100
Notes: 1. If MCLK frequency change under operating, it should need to start power on procedure again. 2. If FSET<2:0> setting are changed, reset function is needed again. By the reset operation, all serial resisters are set to default settings, so it should set serial resister again.
Rev.1.00 Mar 16, 2005 page 20 of 23
M66239FP
After Power-On Procedure
After power-on, M66239FP status is unknown. Following procedure must be done. 1. VCC power-on 2. After Vcc and input clock frequency is stable, set the FSET[2:0]. 3. Reset pulse input. Input more than MCLK 1000 clock cycle from FSET setting is completed to RESET set to "H" level. 4. Serial resister set. 5. After input MCLK clock till PLL lockup time (Tplllock), input twice TR pulse. Input more than 100 cycle MCLK clocks between 1st. TR and 2nd. TR. 6. After that, sync clock will be outputted from M66239FP.
VCC
More than 1000 cycles
MCLK
Input clock frequency is stable tw(RESET) Tplllock
RESET
FSET Serial resister
FSET<2:0> set (refer to page 20)
Serial resister set (refer to page 15 to 17) More than 100 cycles Setting completed
TR
CKO/CKOB/PULSE
tsp tss tsp tss
Note: 1. In case of change the resister set after complete above power on procedure, the new resister set value reflects after the at least more twice TR pulse input. And when changing register 4, for the center frequency purpose to be changed, the locked time of PLL must be wait. Also,there is not a problem even if a trigger signal is entered before the PLL lock after changing register 4. When changing a register except register 4, not need to wait locked time of PLL.
Figure 11 After Power-On Procedure
Rev.1.00 Mar 16, 2005 page 21 of 23
M66239FP
Input Clock Change Sequence
When changing the frequency of the input clock, if being the inside of each range in the frequency range which is specified in page 20, the change of the FSET is unnecessary but the lock of PLL sometimes comes when a frequency is changed even if it is the inside of each range in the frequency range. When the frequency of the input clock changes in each range in the frequency range and PLL comes off the lock condition, it adds that it takes time by locking 10 ms once again. To get a stable output clock, after passing in the PLL lock time in the frequency of input clock or it after phase change, enter TR signal. The output clock which was stable after entry is gotten in the TR signal. About the change of the frequency which exceeds the frequency range which is specified in page 20, for the purpose of FSET[2:0] to be changed, the sequence of power on must be done.
MCLK
TR over 500 ns CKO 10 ms Clock change Clock stable
tsp
The sequence when changing an entry frequency in each range in the frequency range
Figure 12 Input Clock Change Sequence
Rev.1.00 Mar 16, 2005 page 22 of 23
M66239FP
Package Dimensions
JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g
HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
109
72
c1 HE E
c
Reference Symbol
*2
Dimension in Millimeters Min 19.9 19.9 Nom 20.0 20.0 1.4 21.8 21.8 22.0 22.0 22.2 22.2 1.7 0.05 0.17 0.1 0.22 0.20 0.09 0.145 0.125 0 8 0.5 0.08 0.10 1.25 1.25 0.35 0.5 1.0 0.65 0.20 0.15 0.27 Max 20.1 20.1
Terminal cross section
D E A2 HD HE
ZE
144
37
A A1
1 ZD
A2
A
36 Index mark F
bp
c
b1 c
A1
L L1
c1
*3 e y bp x Detail F
e x y ZD ZE L L1
Rev.1.00 Mar 16, 2005 page 23 of 23
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